1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor electrode, and more particularly to a method for manufacturing capacitor lower electrodes of a dynamic random access memory.
2. Description of Related Art
Dynamic random access memory is one kind of semiconductor memory. Each memory cell of a dynamic random access is composed of a field effect transistor and a capacitor, and a source or a drain of the field effect transistor is electrically connected with the capacitor. Capacitors can be categorized into stacked type capacitors and deep trench type capacitors, wherein the stacked type capacitors are directly formed over surfaces of semiconductor substrates containing field effect transistors and the deep trench type capacitors are formed in semiconductor substrates.
As shown in FIGS. 1-4, a conventional method for manufacturing capacitor lower electrodes of a semiconductor memory is provided. At first, the method comprises: fabricating a semiconductor substrate 1a which has a source or a drain of a field effect transistor (not shown) electrically connected with a plurality of conductive plugs 11a; secondly, forming a stacked structure 2a on an upper surface of the semiconductor substrate 1a, wherein the stacked structure 2a includes an insulating oxide layer 21a, a dielectric layer 22a and an insulating nitride layer 23a from bottom to top, and the insulating oxide layer 21a, the dielectric layer 22a and the insulating nitride layer 23a have different etching rates for acid. As shown in FIG. 2, after the stacked structure 2a is formed, partial etching of the insulating oxide layer 21a, the dielectric layer 22a and the insulating nitride layer 23a eventually forms a plurality of trenches 24a, so that the conductive plugs 11a are exposed in the trenches 24a. Then, a conductive metal material 25a is disposed within each trench 24a so as to contact with the conductive plugs 11a; a plurality of U-shaped capacitor lower electrodes 26a are formed in each trench 24a; the capacitor lower electrodes 26a are deposited onto the conductive metal materials 25a; the insulating nitride layer 23a and the capacitor lower electrodes 26a are partially etched as shown in FIG. 3 and FIG. 4; and the dielectric layer 22a is etched and removed.
To improve data storage capacity of memories, density of memory cells must be increased. The solution for solving the problem is to decrease dimensions in a semiconductor fabrication process. However, when dimensions are getting smaller, the semiconductor fabrication, processing of the U-shaped capacitor lower electrodes 26a is getting more difficult, and because the supporting stress becomes lower, it results in being more difficult to fabricate the dielectric layer and capacitor upper electrodes outside the capacitor lower electrodes.